## Serial 2 S Complementer Shift Register

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Transcribed Image Text Q6) Design a serial 2's complementer with a shift register and a flip-flop. The binary number is shifted out from one side and it's 2's complement shifted into the other side of the shift register Get more help from Chegg. What is the maximum frequency at which the counter can operate reliably? 7.Design a serial 2’s complementer with a shift register and a flip - flop. The binary number is shifted out from one side and it’s 2’s complement shifted into the other side of the shift register You've reached the end of your free preview. Want to read the whole page?

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We know that one flip-flop can store one-bit of information. In order to store multiple bits of information, we require multiple flip-flops. The group of flip-flops, which are used to hold (store) the binary data is known as register.

If the register is capable of shifting bits either towards right hand side or towards left hand side is known as shift register. An ‘N’ bit shift register contains ‘N’ flip-flops. Following are the four types of shift registers based on applying inputs and accessing of outputs.

• Serial In − Serial Out shift register
• Serial In − Parallel Out shift register
• Parallel In − Serial Out shift register
• Parallel In − Parallel Out shift register

## Serial In − Serial Out (SISO) Shift Register

The shift register, which allows serial input and produces serial output is known as Serial In – Serial Out (SISO) shift register. The block diagram of 3-bit SISO shift register is shown in the following figure.

This block diagram consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is applied to each one.

In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we can receive the bits serially from the output of right most D flip-flop. Hence, this output is also called as serial output.

### Example

Let us see the working of 3-bit SISO shift register by sending the binary information “011” from LSB to MSB serially at the input.

Assume, initial status of the D flip-flops from leftmost to rightmost is \$Q_{2}Q_{1}Q_{0}=000\$. We can understand the working of 3-bit SISO shift register from the following table.

No of positive edge of ClockSerial InputQ2Q1Q0
0-000
11(LSB)100
21110
30(MSB)011(LSB)
4--01
5---0(MSB)

The initial status of the D flip-flops in the absence of clock signal is \$Q_{2}Q_{1}Q_{0}=000\$. Here, the serial output is coming from \$Q_{0}\$. So, the LSB (1) is received at 3rd positive edge of clock and the MSB (0) is received at 5th positive edge of clock.

### Serial 2 S Complementer Shift Register Download

Therefore, the 3-bit SISO shift register requires five clock pulses in order to produce the valid output. Similarly, the N-bit SISO shift register requires 2N-1 clock pulses in order to shift ‘N’ bit information.

## Serial In - Parallel Out (SIPO) Shift Register

The shift register, which allows serial input and produces parallel output is known as Serial In – Parallel Out (SIPO) shift register. The block diagram of 3-bit SIPO shift register is shown in the following figure.

This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is applied to each one.

In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. In this case, we can access the outputs of each D flip-flop in parallel. So, we will get parallel outputs from this shift register.

### Example

Let us see the working of 3-bit SIPO shift register by sending the binary information “011” from LSB to MSB serially at the input.

Assume, initial status of the D flip-flops from leftmost to rightmost is \$Q_{2}Q_{1}Q_{0}=000\$. Here, \$Q_{2}\$ & \$Q_{0}\$ are MSB & LSB respectively. We can understand the working of 3-bit SIPO shift register from the following table.

No of positive edge of ClockSerial InputQ2(MSB)Q1Q0(LSB)
0-000
11(LSB)100
21110
30(MSB)011

The initial status of the D flip-flops in the absence of clock signal is \$Q_{2}Q_{1}Q_{0}=000\$. The binary information “011” is obtained in parallel at the outputs of D flip-flops for third positive edge of clock.

So, the 3-bit SIPO shift register requires three clock pulses in order to produce the valid output. Similarly, the N-bit SIPO shift register requires N clock pulses in order to shift ‘N’ bit information.

## Parallel In − Serial Out (PISO) Shift Register

The shift register, which allows parallel input and produces serial output is known as Parallel In − Serial Out (PISO) shift register. The block diagram of 3-bit PISO shift register is shown in the following figure.

This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is applied to each one.

In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will get the serial output from the right most D flip-flop.

### Example

Let us see the working of 3-bit PISO shift register by applying the binary information “011” in parallel through preset inputs.

Since the preset inputs are applied before positive edge of Clock, the initial status of the D flip-flops from leftmost to rightmost will be \$Q_{2}Q_{1}Q_{0}=011\$. We can understand the working of 3-bit PISO shift register from the following table.

No of positive edge of ClockQ2Q1Q0
0011(LSB)
1-01
2--0(LSB)

Here, the serial output is coming from \$Q_{0}\$. So, the LSB (1) is received before applying positive edge of clock and the MSB (0) is received at 2nd positive edge of clock.

Therefore, the 3-bit PISO shift register requires two clock pulses in order to produce the valid output. Similarly, the N-bit PISO shift register requires N-1 clock pulses in order to shift ‘N’ bit information.

## Parallel In - Parallel Out (PIPO) Shift Register

The shift register, which allows parallel input and produces parallel output is known as Parallel In − Parallel Out (PIPO) shift register. The block diagram of 3-bit PIPO shift register is shown in the following figure.

This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is applied to each one.

In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. We can apply the parallel inputs through preset or clear. These two are asynchronous inputs. That means, the flip-flops produce the corresponding outputs, based on the values of asynchronous inputs. In this case, the effect of outputs is independent of clock transition. So, we will get the parallel outputs from each D flip-flop.

### Example

Let us see the working of 3-bit PIPO shift register by applying the binary information “011” in parallel through preset inputs.

Since the preset inputs are applied before positive edge of Clock, the initial status of the D flip-flops from leftmost to rightmost will be \$Q_{2}Q_{1}Q_{0}=011\$. So, the binary information “011” is obtained in parallel at the outputs of D flip-flops before applying positive edge of clock.

### Serial 2 S Complementer Shift Register Form

Therefore, the 3-bit PIPO shift register requires zero clock pulses in order to produce the valid output. Similarly, the N-bit PIPO shift register doesn’t require any clock pulse in order to shift ‘N’ bit information.

## 1. Introduction

A shift register is an n-bit register with provision for shifting its stored data by one position at each clock pulse. The logical configuration of a shift register consists of a chain of flip-flops connected in cascade, with the output of one flip-flop connected to the input of the next flip-flop. All flip-flops receive a common clock pulse which causes the shift from one stage to the next. Fig. 1 shows a simple shift register configuration. The new bit to be shifted into one end must be specified, and the bit shifted off the other end is lost unless it is saved externally. Although Fig. 1 shows a right-shift register, the same register can obviously be used for left shifts simply by reversing the sense of the bits. Most shift registers have provision for shifting only in one direction, but some have a control input that allows either left or right shifting to be specified at each clock.

One way to load n bits of data into the flip-flop chain is to load the data one bit each clock cycle using the serial input. Some shift registers also have parallel inputs that can be used to load all n bits in one clock cycle. The output of a shift register can be observed one bit at a time at the serial output, but some shift registers also have parallel outputs for observing all n bits at once.

Shift registers are classified according to three basic considerations: their method of data handling (serial-in serial-out, serial-in parallel-out, and parallel-in serial-out), their direction of data movement (shift right, shift left, and bidirectional), and their bit length. One of the important applications of shift register circuits is in serial computation. Compared to parallel computation, where all bits in a word are processed at the same cycle, serial computation process words in one bit per cycle. Therefore, serial computation is slower, but it has the advantage of requiring less hardware and wiring. A serial adder will be built in this experiment as an example.

## 2. Objectives

Students are expected to understand various data handling methods in shift registers and their usage.

## 3. Experiment

### Serial 2 S Complementer Shift Register Online

Use two 7474 dual flip-flops to connect a serial-in, parallel-out shift register as shown in Fig. 1. Connect L1–L4 to four LEDs (with current-limiting resistors), SW1 and SW2 to switches, and CLK to a pulser. Initially, set SW2 to logic 1. Switch SW2 being at logic 1 clears all flip-flops. Now set SW1 to logic 1 and SW2 to logic 0. Push the pulser button several times to allow more logic 1 to be shifted into the shift register. Change SW1 to logic 0 and repeat the experiment again.

### Serial 2 S Complementer Shift Register Download

Now use the above circuit to build a pseudo-random binary sequence generator as shown in Fig. 2. This binary sequence generator will display a random output (repeats every 2n–1 bits, where n is the number of flip-flops used in the shift register). The IC 7486 provides the exclusive-OR needed in the circuit. To start the sequence generator, set the initial state of the shift register to 0001 by setting the switch SW1 to logic 1. Then change SW1 to logic 0 as this will release the control input. Now apply the clock and record the output in a table. Does the output show randomness? Does the output repeat after 15 pulses?

### 3.3. Serial Adder

A serial adder adds bits adds a pair of binary numbers serially with a simple full adder. The carry out of the full adder is transferred into a D flip-flop and the output of this carry flip-flop is then used as the input carry for the next pair of significant bits. Fig. 3 illustrates an example of serial addition.

Fig. 4. shows the block diagram design of a serial adder. The two binary numbers to be added serially are stored in two shift registers (using two 74164, 8-bit serial-in, parallel-out shift registers). Bits are added one pair at a time through a single full adder (such as the one in Experiment 2) The carry out of the full adder is transferred into a D flip-flop. The output of this carry flip-flop is then used as the input carry for the next pair of significant bits. The sum output from the full adder is transferred into register A as the contents of the register are shifted out.

### Serial 2 S Complementer Shift Register Online

Gunsc0unter \$trike 1.6. To perform the addition, the following steps are used.

1. Shift the first 8-bit augend into A (remember to shift in LSB first) and addend into B. This is done by performing the following steps:

1. Clear registers A and B, and the D flip-flop. The registers and flip-flop have a clear input that can be used to accomplish this task.

2. Shift the augend through the serial input. For 8-bit registers, one bit will be shifted into register B for each of eight clock cycles, least significant bit first. (Since registers A and B initially contain all zeroes, the output of the full adder will be 0 for both the sum and carry outputs during these clock cycles. You can either load these zeroes into register A or just leave A unchanged. In either case, after eight clock cycles, Register B will contain one operand and register A will contain all zeroes.

3. Shift the addend through the serial input. This is actually two tasks performed at once. While the addend is being shifted into register B, the augend is being shifted out of B and into register A. To understand how this occurs, recall that register A contains all zeroes. Whatever bit is being shifted out of B is being added to the zero in the least significant bit of A. The sum will just be the least significant bit of B, which is shifted into the most significant position of register A. After eight clock cycles, register A contains the augend and register B contains the addend.

2. Clear the D flip-flop and run the adder for eight cycles to obtain the sum.

Table 1 shows the values in registers A and B when the data values 01011101 and 10011110 are added together.

Table 1: Trace of the serial adder
Serial InputRegister ARegister BD FFComments
X00000000000000000Clear A, B, D
100000000100000000
000000000010000000
100000000101000000
100000000110100000
100000000111010000
000000000011101000
100000000101110100
000000000010111010Augend in B; 0 in A
0100000000010111000+1=1
101000000100101110
110100000110010110
111010000111001010
111101000111100100
001110100011110010
010111010001111000
101011101100111100Augend in A; Addend in B
X10101110X10011110C=0, S=1
X11010111XX1001110C=0, S=1
X01101011XXX100111C=1, S=0
X10110101XXXX10011C=1, S=1
X11011010XXXXX1001C=1, S=1
X11101101XXXXXX100C=0, S=1
X11110110XXXXXXX10C=0, S=1
X11111011XXXXXXXX0Sum in A

## 4. Prelab

1. Show the sequence generated by the pseudo-random sequence generator.
2. Study the operation of the 74164.
3. Draw a circuit diagram of the serial adder showing the connections for all the components.
4. What is the maximum clock speed for the adder circuit of part 3.3? Assume worst case delays and 74LSXX type logic.

## 5. Equipment and parts required.

• Protoboard
• Two TTL D Flip-Flops (7474)
• One TTL NAND (7400)
• One TTL inverter (7404)
• One TTL XOR (7486)
• Two TTL Shift registers (74164)
• Eight LEDs and limiting resistors

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